The present invention relates in general to complementary metal oxide semiconductor (CMOS) technology, and more specifically, to vertical transistors with back bias and reduced parasitic capacitance.
CMOS technology is used to construct integrated circuits such as microprocessors, microcontrollers, static random access memory (RAM) and other digital logic circuits. A basic component of CMOS designs is metal oxide semiconductor field effect transistors (MOSFETs). As MOSFETs are scaled to smaller dimensions, various designs and techniques are employed to improve device performance. Vertical transistors (VFET), in which source/drain regions are arranged on opposing ends of a vertical channel region, are attractive candidates for scaling to smaller dimensions.